MODELING AND SIMULATION OF A CYCLIC DIGITAL-TO-ANALOG CONVERTER USING VHDL-AMS

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Title: MODELING AND SIMULATION OF A CYCLIC DIGITAL-TO-ANALOG CONVERTER USING VHDL-AMS
Author: VAIDYANATHAN, GAYATHRI
Description: As is well known, the transistor density is ever increasing and so is the demand for wireless devices. Thus, one of the booming areas in the field of integrated circuit design is Systems-on-Chip (SOC) design. SOCs are becoming highly complex, and have digital, mixed-signal, and analog components to satisfy the growing demands of communication applications. As mentioned above, digital circuits may be modeled using VHDL, and the procedure for defining digital model in VHDL is well known. But there is not a well defined method for modeling mixed-signal systems. The modeling of analog and mixed signal components in a top-down methodology is an intensive task and hence, effective modeling of these components can drastically decrease the time taken for design and verification of the complex SOCs. This, in turn will decrease the time-to-market. In this thesis, we propose a top-down design methodology to model a cyclic digital-toanalog converter (DAC). We have chosen the cyclic DAC because of the low-power alternatives and compactness in terms of circuit when compared to other DAC architectures. We have shown how the top-down design methodology can reduce the simulation time of the mixed-signal system at the top-level of abstraction without compensating much on accuracy of the model. The DAC is modeled and simulated at various levels of abstraction and fidelity, using VHDL-AMS. This generic DAC can be used to model a range of inputs that are specified by the user, and which conforms to the desired system specifications.
Permanent Link: http://rave.ohiolink.edu/etdc/view?acc_num=ucin1140648632
http://hdl.handle.net/2374.OX/10440
Date: 2006

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