STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS

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Title:	STATIC TIMING ANALYSIS OF MICROPROCESSORS WITH EMPHASIS ON HEURISTICS
Author:	Krishnamurthy, Sivasubramaniam T.
Description:	As designers build complex digital circuits with ever diminishing device sizes, there is a need to obtain fast circuits with low hardware overhead. Critical path is the longest sensitizable path in a digital logic circuit which determines the operating frequency of the circuit. Static timing analyzers enumerate critical paths in a circuit and determine the optimal operating frequency. This work presents a static timing analyzer that makes use of an ATPG technique based on the PODEM engine. To improve the efficiency of the technique, a partitioning scheme is used in the path sensitization subroutine to reduce the search space. The results from this implementation for the ISCAS ’85 and ’89 benchmarks demonstrates performance improvements.
Permanent Link:	http://rave.ohiolink.edu/etdc/view?acc_num=case1201299462 http://hdl.handle.net/2374.OX/16192
Date:	2008

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