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2 GHz transmitter design based on 0.18 UM CMOS process and its linearization and 8 GHz transceiver design based on 0.25 UM SiGe bipolar process using GSML method
| Title: | 2 GHz transmitter design based on 0.18 UM CMOS process and its linearization and 8 GHz transceiver design based on 0.25 UM SiGe bipolar process using GSML method |
| Author: | Lee, Jongsoo |
| Description: | 2 GHz CMOS transmitter was designed and implemented. The architecture of the CMOS transmitter integrated I/Q modulator, a variable-gain pre-amplifier, two LO buffers and a polyphase filter. The baseband which was generated from a FPGA board was upconverted by the transmitter. The output power of the upconverted RF signal was controlled in the transmitter using a gain-controlled stage of the current steering structure which featured in the preamplifier. In this work, digital predistortion technique with I/Q signal balancing process was used to linearize a CMOS transmitter and provide a harmonic free output spectrum. Correction odd harmonics of the baseband signal were generated and injected at the baseband input ports along with an original baseband signal. It was verified that well-controlled odd harmonics of the baseband signal attenuate unwanted harmonics products located in the RF band and generate a harmonic free output spectrum. A 8 GHz SiGe bipolar transceiver was designed and implemented. The transceiver integrated a VCO, a Darlington-amplifier, a VGDA, and up and down conversion mixers, which were all independently implemented. Both mixers included baluns inside each chip. In this work, a practical layout method called Ground-Shield-Microstrip-Lines (GSML) was proposed to take care of transmission line loss at a fairly high frequency. GSML provide a simplified parasitic model because the lines are shielded from the low resistivity silicon substrate which causes complicated parasitic networks. The accurate and reliable GSML layout methodology was used in the design of a 8 GHz Transceiver. The ground shield layer is conformed to the circuit such that the interconnection lines are shielded from the low resistive silicon substrate. This layout methodology has the advangtage of greatly simplifying the estimation of the parasitic networks for the interconnection lines at the expense of introducing trivial amount of loss. In this work, the GSML method replaced the post layout simulation and reduced iteration times, increasing efficiency in the design and optimization of the circuit. |
| Permanent Link: |
http://rave.ohiolink.edu/etdc/view?acc_num=osu1198774439
http://hdl.handle.net/2374.OX/7721 |
| Date: | 2008 |
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